CAT24C21
Transmit ? Only Mode: (DDC1)
Upon power ? up, the CAT24C21 will output valid data
only after it has been initialized. During initialization, data
will not be available until after the first nine clocks are sent
to the device (Figure 3). The starting address for the
transmit ? only mode can be determined during initialization.
If the SDA pin is high during the first eight clocks, the
starting address will be 7FH. If the SDA pin is low during the
first eight clocks, the starting address will be 00H. During
the ninth clock, SDA will be in the high impedance state.
Transmit ? Only Mode
Data is transmitted in 8 bit words with the most significant
bit first, followed by a 9th ‘don’t care’ bit which will be in
the high impedance state (Figure 4). The CAT24C21 will
continuously sequence through the entire memory array as
long as VCLK is present and no falling edges on SCL are
detected. When the maximum address (7FH) is reached,
addressing will wrap around to the zero location (00H) and
transmitting will continue. The bi ? directional mode clock
(SCL) pin must be held high for the device to remain in the
transmit ? only mode.
Bi ? Directional Mode
SCL
T VHZ
SDA
VCLK
Figure 2. Mode Transition
SCL
SDA at high impedance for 9 clock cycles
SDA
Bit8
Bit7
Bit6
Bit5
Bit4
VCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
T VPU
T VAA
Figure 3. Device Initialization for Transmit ? only Mode
SCL must remain high for transmit ? only mode
SCL
Don’t
SDA
Bit8
(MSB)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1 Bit8
(LSB) Care
Bit7
VCLK
T VHIGH
T VLOW
Figure 4. Transmit ? Only Mode
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相关代理商/技术参数
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CAT24C21WI-T3 制造商:ON Semiconductor 功能描述:1K DUAL MODE SERIAL EEPROM - Tape and Reel
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